cd4027a typ s cos/mos dual j-k master-slave flip-flop the rca-cd4027a is a single monolithic chip integrated circuit containing two iden- tical complementary-symmetry j-k master- slave flip-flops_ each flip-flop has provisions for individual j. k. set. reset. and clock in- put signals_ buffered 0 and q signals are provided as outputs_ this input-output ar- rangement provides for compatible opera- tion with the rca-cd4013a dual d-type flip-flop_ the cd4027 a is useful in performing con- trol. register. and toggle functions_ logic levels present at the j and k inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse_ set and reset functions are independent of the clock and are initiated when a high level signal is pres- ent at either the set or reset input_ maximum ratings. absolute-maximum values: storage-temperature range (tug) __________ . _ .. ___ .... _ ....? _ -65 to +16o"c operating-temperature range (t a): package types d. f. h' . __ . ? . . ? . . . . ? . . . . . . . . . . . . . . . . ? . . . .. -55 to +126c package type e -40 to +85c dc supply-voltage range. (vdd) (voltages referenced to vss terminall: ?..................?...?.... _ ? -0.5 to +16 v power dissipation per package (po): for t a - -40 to +60c (package type e) .. . ? . . . . . . . ? . ? ? . . . . . . . . . 600 mw for t a ? +60 to +85c (package type' e) ?????.? derate linearly at 12 mwfc to 200 mw for t a ? -65 to +l00"c (package types d. f) ...........?.....??.?. 600 mw for t a ? +100 to +126"c (package types d. f) .... derate linearly at 12 mwfc to 200 mw device dissipation per output transistor fort a ? full package-temperature range (all package types) ? . ? ? . ? 100 mw input voltage range. all inputs. . . . . . . . . . ? . ? . . . . . ? . . . ? ? .. -0.6 to v dd +0.6 v lead temperature (during soldering): at distance 1/16:1: 1132 inch (1.59:1: 0.79 mm) from case for 10 s max ??????..?..?. , +266"c recommended operating conditions at ta = 2!tc, except. noted. for maximum reliability, nominal operating condition. should be selected so that operation is always within the following ranges. limits characteristic v dd d. f, h' e (v) packages package min. max. min. max. supply-voltage range (for ta = full 3 12 3 12 package-temperature range) data setup time. ts 5 150 - 200 - 10 50 75 - - clock pulse width. tw 5 330 - 500 - 10 110 165 - - clock input frequency (toggle 5 1.5 dc 1 mode) fcl 10 dc 4.5 3 clock rise or fall time. trcl. tfcl 5 - 15 - 15 10 - 5 - 5 set or reset pulse width. tw 5 200 - 300 - 10 80 120 - - units v ns ns mhz /-is ns 'if more than one unit is cascaded in a parallel clocked operation, tpl should be made les5 than or equal to the sum of the fixed propagation delay time at 15 pf and the transition time of the output driving stage for the estimated capacitive load. ? cd4027a functional diagram these types are supplied in l6-lead hermetic dual-in-line ceramic packages (0 and f suffixes). l6-lead dual-in-line plastic pack- age (e suffix). l6-lead ceramic flat package (k suffix). and in chip form (h suffix). features: ? set-reset capability ? static flip-flop operation-retains state indefinitely with clock level either "high" or "low" ? medium-speed operation-l0 mhz (typ.) clock toggle rate at 10v ? ouiescent current specified to 15 v ? maximum input leakage of 1 /-ia at 15 v (full package-temperature range) ? 1-v noise margin (full package-tempera- ture range) applications ? registers. counters, control circuits fig. 1 - typical n-channel drllin characteristics. 496 ______________________________________________________________________ __
static electrical characteristics limits at indit;a i ~u temi"t:ha 1 u"~:; (oci conditions d. f. h --- e package .- characteristics lv, iv ,n ivdd +z5 +!5 +125 -40 (vi (vi (vi -55 i typ. i limit typ. ilimit 5 1 10.005 1 60 10 0.01 10 quiescent device 10 2 10.0q5 2 120 20 o.m 20 current, 'l max. 15 25 0.5 25 1000 250 2.5 250 output voltage: 05 o typ . c 05 max low level, vol 0.10 10 0.05 max high level - 0.5 5 5 typ 4.95 min voh olc 10 10 typ .. 9.95 min noise immunity: ,4.2 5 225 typ., inputs low, - v nl . typ. inputs high 0.8 - 5 ,typ.; v nh 1 10 4.5 typ.; 3 min noise margin' 4.5 5 1 min inputs low, v nml inputs high, 1 min v nmh 1 10 1m output dnve current. n channel 5 ~:~~ 1 05 0.35 0.35 1 03 (slnkl. 105 - 10 25 1 075 072 2.5 06 ion min. pchannel 4 5 -031 -0.5 -0.25 :-0 175 -0.17 0.5 -014 (source)' i 'opmin. 9.5 10 -0.8 -13 .n",,, .n"<;1 -0.4 -1.3 -0.33 v. input leakage current, any l'l'i'h input 15 10- 5 typ., 1 max i 0"..0+ _________ -... _____________ +-_--, ci cl ? clock f'..... 1 f'..... 1 3031~ rl~ *a~in~ss pllqt[cted by cosiiios protection network fig. 2 -logic diagram & truth table for cd4027a (one of two identical j-k flip flops). prisent state inputs ojtpu cl a 0 , ? 0 0 ./ ? 0 0 0 / ? , 0 0 f logic '-highlev[l logic 0- low l[v[l units +85 140 280 ija 2500 v v v 024 05 ma -01;/ -0.27 ija n[xt stat[ __ mochangl 92cm j7188r4 cd4027 a typ s ...... - to - souace \iol15 '''os' " 10 12.' " orain - to - $oi..fk: 'oq..ts iyosi fig. 4 - minimum n-channel drain characteristics. oaain - to - source volts (yos) fig. 5 - mmimum p-channel drain characteristics. loao capacit"nce cc l )-" fig. 6 - typical propagation delay time vs. c l . 497
cd4027a typ s dynamic electrical characteristics at 1a = 25'c, inputt" t f = 20 ns, c l = 75 pf, r l = 2()() kf1. limits characteristic v dd d. f. h e units packages package (v) min. typ. propagation delay time: clock to a 5 - 200 or 6 outputs tphl. tplh 10 - 100 set to a or reset to a, 5 - 175 tplh 10 - 75 set to a or reset to 0, 5 - 175 tphl 10 - 75 transition time 5 - 75 tthl. ttlh 10 - 50 maximum clock input 5 1.5 3 frequency (toggle 10 4.5 8 mode)tcl minimum clock pulse 5 - 165 width,t w 10 - 65 minimum set or 5 - 125 reset pulse width, 10 - 50 tw minimum data setup 5 - 70 time, ts 10 - 25 clock rise or fall 5 - - time. trcl' tfcl 10 - - average input any capacitance, c, input - 5 inputovdo outputs vdd'~ ~ o _ vnl not[ tut "", one input. vss with 01l4(" inputs at voo 011 vss fig. '0 - noise immunity test circuit. max. min. typ. max. 400 - 150 400 ns 200 - 75 150 225 - 175 350 110 75 150 ns - 225 - 175 350 110 75 150 ns - 125 - 75 250 70 - 50 140 ns - 1 3 - - 3 8 - mhz 330 - 165 500 110 - 65 165 ns 200 - 125 300 80 - 50 120 ns 150 - 70 200 50 - 25 75 ns 15 - - 15 5 - 5 us - - - 5 - pf v~npuo' ,~ i~::,::~ vss to iidth voo &nii."s cqmii[ct all uelusm inputs to [ith[a veo 011 vss vss fig. " - input leeke(jl1 current test circuit. ii i! ii oft "!emt.oii 10 fig.7 - typical transition time vi. cl. fig.8 - typical maximum clock input frequency vs. supply voltage. _nt tl'ipuat_,t.iz5 'c 'nput ".' ?? 20 .. , . ip-o' cancltanct: ie "'5o!! ~'o' 111111 iii ~ ijlo"" "j 50 tl lo ' ..... u _n v .", " ~ is"~ a ~ ~ p r .,2 a i i ., . ,01 10' 10 10 . , input 'ft[qu[ncyc ?? '- h, fig.9 - typical dissipation characteristics. o vss inputs fig. , 2 - quiescent d8vice current fljst circuit. 498 ____________________________________________________________________ __
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